1. Field of the Invention
The invention relates in general to a sequential memory and an accessing method thereof, and more particularly to a sequential memory and an accessing method thereof capable of saving the operation time and reducing the operation power.
2. Description of the Related Art
Memories have been currently used in the field of data storage widely. The memory has a plurality of memory cells disposed in an array usually. Each row of memory cells corresponds to one word line, and each column of memory cells corresponds to one bit line. Each memory cell includes a transistor, which has a first terminal coupled to a bit line, a second terminal coupled to another bit line, and a control terminal coupled to a corresponding word line.
The conventional memory operates in several steps, which usually include a charge step, a sense step and a discharge step. The discharge step is very important. If no discharge step is performed to clear the residual charges in the previous access period, initial voltages of the first terminal and the second terminal of the transistor may be different from each other in the current access period. In addition, the memory cell may have the residual charges after being read or programmed, thereby causing the leakage current or other unpredictable errors.
FIG. 1 shows a timing chart when a conventional memory is being read. As shown in the example of FIG. 1, an nth memory cell in a row of memory cells is read, wherein n is a positive integer. Usually, before the memory operates, a pre-discharge period (not shown), in which voltage levels of first terminals and second terminals of transistors in all the memory cells are pulled down to a low level voltage (i.e., a ground voltage), exists.
When the data stored in the nth memory cell is read, that is, in the nth reading period Tn, a bit line timing control bl_clk of a bit line corresponding to the nth memory cell has a low level voltage between the time instants t0 and t1 and the nth memory cell does not operate, and then has a high level voltage between the time instants t1 and t4, and the nth memory cell is being accessed.
In the charge period from the time instants t1 to t2, the bit line (drain side) of the nth memory cell is charged, and the voltage level of the charge pulse “charge” is transformed into the high level voltage. Next, in the sense period from the time instants t2 to t3, the nth memory cell is sensed (data evaluation), and the voltage level of a sense pulse sa_en is transformed into the high level voltage. Thereafter, in the discharge period from the time instants t3 to t4, the bit line of the nth memory cell is discharged, and the voltage level of a discharge pulse “discharge” is transformed into the high level voltage.
In addition, when the conventional memory is operating, it is also possible to perform the discharge operation followed by the charge and sense operations. If one row of memories has m memory cells, m discharge periods are required to read/program the row of memories. When the memory is being verified and if the verification error occurs, the m discharge periods have to be spent to read or program the memories again, thereby wasting a lot of time and disabling the memories from operating at the high speed. In the meanwhile the memory operation power consumption raises substantially.
In addition, when the number of memory cells corresponding to the same bit line increases, the overall capacitance of the bit line also increases. Consequently, the discharge period (i.e., the time instants t3 to t4 in FIG. 1) of the memory cells increases, and the time of reading/programming the memory cells is thus lengthened, thereby wasting a longer period of operation time. Besides, when the number of memory cells corresponding to the same bit line increases, the currents we need to charge the overall capacitance on the bit line also increase, thereby wasting more power consumption.